The present invention relates to a terminal allocation system in a printed board, an LSI and the like and more particularly to a terminal allocation system for obtaining excellent electrical characteristics of the printed board, the LSI and the like.
When the electronic device is designed hierarchically, a technique of the prior art in allocating signal lines to terminals, for example, is disclosed in the Japanese Patent Application Laid-Open Number SHO 59-197189, and is well-known. The prior art of this sort is an allocation system in which the total wiring length of the whole signal lines from lower hierarchical components through terminals is made shortest when the signal lines are allocated to terminals for the purpose of reducing the unconnected pin to pin ratio. When the operation of the electronic device is at comparatively low speed, it is not required to consider wiring length restrictive conditions on signal lines by the signal frequency, the number of loads and so on. Therefore, it was possible to conduct terminal allocation of signal lines having good electrical characteristics.
Generally, it is required to consider wiring length restrictive conditions of signal lines in order to make the electronic device operate at a higher speed.
In said prior art, however, no consideration is given to wiring length restrictive conditions of respective signal lines. Thus, said prior art has a drawback that it is not possible to conduct terminal allocation which satisfies wiring length restrictive conditions of signal lines and has good electrical characteristics when the operation of the electronic device is at high speed in a hierarchically designed electronic device.
The above said problems will be described in a more concrete manner with reference to FIG. 7. In FIG. 7, it is assumed that signal points A1 and B1 of hatched components and signal points A2 and B2 of components in an upper hierarchy of those components are connected with each other by means of signal lines A and B; two terminals T.sub.1 and T.sub.2 are designated as terminals for connection between both hierarchies, and wiring lengths of the signal lines A and B are restricted to LA max=10 cm and LB max=5 cm, respectively.
When the signal line A is allocated to the terminal T.sub.1 and the signal line B is allocated to the terminal T.sub.2, the wiring length of the whole signal lines becomes LA+LB=13 cm as shown in the case 1 in FIG. 7. Also, when the signal line A is allocated to the terminal T.sub.2 and the signal line B is allocated to the terminal T.sub.1, the wiring length of the whole signal lines becomes LA+LB=15 cm as shown in the case 2 in FIG. 7. Since the total wiring length in the case 1 is shorter, the wiring of the case 1 is selected in the abovementioned prior art. However, the wiring length LB of the signal line B becomes longer than LB max, thus good electrical characteristics are not obtainable.